1. Field of the Invention
The present invention relates to a semiconductor package for connecting an integrated circuit die to a printed wiring board. Further, the invention relates to a method of manufacturing such a semiconductor package.
2. Description of the Related Technology
One of the challenges in the packaging of advanced semiconductor devices is to reduce the packaging process stress in the package. The stress generated in a package can come from various sources. One of the sources of the stress is the difference in the coefficient of thermal expansions (CTE) of the different materials used for packaging. A typical packaged device experiences exposure to different temperatures during its entire operational life time. During each of such temperature variations, the different materials in the package expand or contract at different rates depending on whether the package is heated up or cooled down. The differential expansion of the various packaging layers can cause severe stress on the semiconductor device.
In U.S. Pat. No. 6,173,489 B1 “stress deflectors” are introduced in the substrate by isolating a portion of the substrate underneath the bond pads of the flip chip so that the integrated circuit is allowed to float and expand at a different rate. Therefore voids are introduced to allow the part of the substrate underneath the flip chip to float. This concept can be used for printed wiring boards to allow the package to float with respect to the printed wiring board (PWB).
In WO00/11716 stress is reduced on printed wiring boards with a void or a constructive void.
The disadvantage of the approaches presented in U.S. Pat. No. 6,173,489 and WO00/11716 is the introduction of a void in the PWB. This requires additional process steps. Furthermore, presence of voids or constructive voids in the printed circuit board (PCB) or the substrate may result in paths for moisture to be trapped. This can cause permanent damage to the package or the board during the melting of the soldered interconnections. Furthermore, the concept of using an insert piece to create a set of floating bond pads requires extra process steps.
In U.S. Pat. No. 5,250,839 a thermal stress absorber is used for laminated leadframe devices to absorb the thermal disparity between two parts of the leadframe. This approach is used however only for the stresses arising from the leadframe manufacturing due to welding of the two metals. The thermal disparity in the operation of the package cannot be absorbed since the laminated leadframe is overmolded as a part of packaging process.
A conventional flip chip package comprises an interposer substrate which is with a first side electrically connected to an integrated circuit die. The connection is for instance done with the aid of solder interconnections connecting bond pads on the die with corresponding bond pads on a first side of the interposer substrate. The thus formed flip chip assembly is preferably under filled, which involves dispensing a liquid polymer adjacent to one edge of the assembled integrated circuit and allowing the polymer material to flow underneath the assembly due to capillary forces. The assembly is then exposed to higher temperatures to allow cross linking of the polymer which renders it solid and which allows the stresses in the assembly to be redistributed over a larger area of the integrated circuit.
In general, the flip chip packages are packaged with ceramic or plastic substrates. Ceramic materials have a CTE which is close to that of silicon and hence the stress induced on an integrated circuit die assembled on a ceramic substrate is low. In combination with the use of an under fill material, these combinations produce a very reliable soldered interconnection at the flip chip level.
Problems arise when a second side of the interposer substrate is electrically connected to a printed wiring board. The connection is for instance done with the aid of solder joints connecting bond pads on the PWB with corresponding bond pads on the interposer substrate. When such a ceramic flip chip package is assembled on a conventional PWB there is usually a very large CTE mismatch between the package and the PWB. In case of a ceramic flip chip package, the CTE is typically about 3-7 ppm/° C., while the CTE of a conventional PWB is typically about 16-18 ppm/° C. When this assembly is subjected to temperature variations, the solder joints connecting the package to the PWB fail very quickly. These situations require use of special and expensive board level interconnection solutions.
Conversely, the interposer substrate of the flip chip package can also be made of a material with a CTE closer to that of the PWB, for instance of plastic composite material. This substrate results in a better board level interconnection reliability and a reduction of the stress between the PWB and interposer substrate. However, the CTE mismatch between the integrated circuit die and the interposer substrate will now be much greater than in the case of a ceramic substrate which will require the use of under fill material that may induce a high amount of stress on the integrated circuit die.
The continued reduction of the transistor dimensions at the device level has resulted in reduced interconnect dimensions, especially on the die. For improving the performance of semiconductor devices, new dielectric materials with lower dielectric constant (commonly referred to as low K dielectrics) are currently in use. Ultra low K back end of line (BEOL) on the die often uses porous dielectric materials with low mechanical strength. As these low k dielectrics have reduced mechanical strength compared to conventional dielectric materials, they are more susceptible to failures under stress. Flip chip packaging for ultra low K devices requires a low stress packaging approach. Any excess stress imposed by the packaging process results in damage to the BEOL stack resulting in the device failure. Hence the packaging of the die requires reduction of the overall stress in the package for improved package reliability. One of the most important sources of the stress is the difference in the coefficient of thermal expansions (CTE) of the different materials used for packaging.
Along with the introduction of the ultra low K BEOL, the interconnect dimensions are also shrinking down for instance, down to about 20 micron for peripheral array devices, which requires use of fine pitch wiring to route out all the interconnects from the die level to the board level interconnects.